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- Re: Extending IPv4 with source translation/source privacy.
[snip]
[snip]
A presumably very dumb argument from an ignorant: You are apparently
modifying a standard and that's generally not a good idea IMHO except
though the standardization gremium. I can't strongly argue in the
field of data transmission because my knowledge there is extremely
poor, but in the presumably akin field of standardization of
- Re: Extending IPv4 with source translation/source privacy.
(snip)
There is already a system for doing this, though not at the IP level.
It is available for those protocols for which it seems useful.
It would be a lot of work, and little gain, to do it for
protocols that it isn't needed for.
-- glen
- Re: Renamer Port Reduction
Possibly relevant anecdotes:
At SC09, in some session about how to teach parallel programming, the
speaker asked the audience who found parallel programming easier than
sequential. I was the only person who raised my hand. I distinctly
remember how, in one of my first programming class exercises at McGill,
- Re: Renamer Port Reduction
Not asymptotically.
Extrapolating trends we might build machines that are not multithreaded
- that when they take a cache miss, don't switch to a different thread,
but just block.
I tried to formulate a rule of thumb: Q: when do you add a second
core rather than doubling the number of threads? A: when the wire cost
- Re: New High Bandwidth Supercomputer
I do like it, particularly that optical hub with 48x7=336 bidirectional
10 Gbit/s links. :-)
Terje
- Re: Extending IPv4 with source translation/source privacy.
Though to further clearify this potential kink in the cable... it
would/could only be a kink in the cable for ipv4... not for newly designed
protocols
perhaps ipv6 can still be modified or future protocols.
Perhaps those future protocols could reserve a part of the address space for
"fake addresses" for privacy.
- Re: Renamer Port Reduction
I believe some of us do, i.e. after enough years hand-optimizing asm
code we develop a feel for what is hard and what is easy for the cpu to
do. Some of my own internal rules are obviously not exactly right, but
close enough to mostly help get a good result.
When I stop to think about it, like now, I feel that it is similar to
- Re: Extending IPv4 with source translation/source privacy.
Another way of looking at this idea is from the point of "address
translation" also known as NAT.
I'm a bit rusty about NAT but as far as I remember NAT works by using public
available resources like public ip addresses, and public ports and tries
to attach a single public ip address and multiple public ports to multiple
- Re: Extending IPv4 with source translation/source privacy.
Some furher thoughts/clearifications on this idea:
The idea assumes that at each router a modest ammount of traffic passes it.
So the idea assumes that the router will see less than half of the total ip
range go past it.
The idea would fail if 50% of the total internet ip range passes a single
router and all ip's desire privacy option.
- Re: Renamer Port Reduction
Which means that we're quite a bit beyond the point you told me you
expected many years ago, i.e. "calculations are free, getting the data
in & out is the only real cost".
If you have to load the real data anyway, having a look-aside buffer
(i.e. cache) to speed it up slightly means that you're simply doing more
- Extending IPv4 with source translation/source privacy.
Hello,
The internet protocol version 4 could be extended with source
translation/source privacy.
The idea is as follows:
The ip.source is translated into something else/arbitrary along the path's
routers to it's destination.
Each router selects a random available ip from a table which is to replace
- New High Bandwidth Supercomputer
[link]
Maybe all you whiners out there will like this one. :-)
The video link in the article doesn't seem to work. I'll have to see if
I can locate it.
- Re: Renamer Port Reduction
As an interesting side topic, and way off the original intent of this
thread.....
I have found it interesting that one can build a trace cache machine
for a RISC design point with a 20 Gate pipestage in about 6-7 pipe
stages, or about 8-9 pipe stages for a 16 gate pipe. However, all the
16-gate x86 pipelines (P-Pro and derivatives, and Athlon and Opteron
- Re: Renamer Port Reduction
True. You have to trade off the increased leakage due to the decreased
space efficiency (which Mitch mentioned in another post). You leak (most)
all the time, while clock gating often means you only pay dynamic power as
needed...
Ned
- Re: Renamer Port Reduction
I read comments like this in discussions like this and I wonder: why
don't we program the way that computer architects think?
I'm sure that, to understand the real answer to a question like that,
I'd have to go through the experience of trying to be an architect
myself. There isn't enough time left, and I probably never had the